DRAM architecture

A single server has memory which is composed of multiple DRAM dies.

Connecting DRAM to CPUs

Memory is connected to the host CPU through memory channels.

In HBM, each DRAM die has its own memory channel:

---
title: HBM
---
graph LR
	A[DRAM die] --> M[Memory Channel]
	M --> C[CPU]

In standard DDR DIMMs, multiple dies share a single memory channel.

---
title: DDR
---
graph LR
	A[DRAM die] --> M[Memory Channel]
	B[DRAM die] --> M[Memory Channel]
	D[DRAM die] --> M[Memory Channel]
	E[DRAM die] --> M[Memory Channel]
	M --> C[CPU]

Inside a DRAM die

Cells are the lowest-level containers of information in DRAM.

Cells are grouped into mats.

Mats have columns and rows.

• Cells in a column are connected to a single bitline sense amplifier (BLSA).
• Rows are selected using a sub-wordline driver (SWD)

Mats are grouped into subarrays, and subarrays are grouped into subbanks. A collection of subbanks forms a bank.

Banks are independently controllable even though they all share a single memory channel.

DQ pins (DQs) are the data pins from which DRAM data is sent out.

Between the DQs and the BLSAs is a column decoder which routes BLSAs to DQs. Column remaps are implemented here during manufacturing to improve yield.¹

Footnotes

1. Predicting Future-System Reliability with a Component-Level DRAM Fault Model | Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture ↩