LingKun LX2

LX2 is the custom ARMv9 CPU used in the LineShine supercomputer. It has:

• 2 dies integrated into a single socket
• 304 cores total
• 1.55 GHz clock
• 60.3 TF FP64 (matrix)
  • 128 FLOPS/cycle/core
  • 64 FMAs/cycle/core
  • 1x 8x8 FMOPA (512-bit SME)
• 32 GB of HBM2e¹ (8x 4 GB stacks)
  • 4 TB/s theoretical
  • 450 GB/s per stack measured²
• 256 GB DDR
  • 125 GB/s measured per die²
  • This is probably DDR5 (dual-channel DDR5-8800 or quad-channel DDR5-6400)
• 690 W³

Each core has 32 KB L1 instruction cache and 32 KB L1 data cache. ³

Groups of 38 cores are associated with a cluster with a shared 28.5 MB L2 cache.³

Footnotes

1. Assumed based on the specs of 8 stacks, 32 GB total, and 4 TB/s from https://arxiv.org/html/2604.15821v1. The authors deliberately exclude the HBM generation (and DDR generation) from the literature. ↩

2. [2605.08633] Transforming the Use of Earth Observation Data: Exascale Training of a Generative Compression Model with Historical Priors for up to 10,000x Data Reduction ↩ ↩²

3. See the Dongarra report, “Report on the Chinese LineShine System” (Tech Report No. ICL-UT-26-01) published June 23, 2026. ↩ ↩² ↩³